Multilevel Blocking in Complex Iteration Spaces

This paper presents a new unified method for simultaneously tiling the register and cache levels of the memory hierarchy. We will focus on the code transformation phase of tiling. Our algorithm uses strip-mining and loop interchange on all memory hierarchy levels to determine the tiles as usual, and, afterwards, and due to the special characteristics of the register level, we apply index set splitting, fully unrolling and unnecessary load/store elimination. We propose a technique to perform the loop interchange in non-convex iteration spaces that computes the loop bounds exactly and we also present an order in which to perform index set splitting that guaranties that each loop in the nest will be processed only once and also avoids code explosion. The performance of the memory hierarchy obtained with the method presented in this paper is substantially higher than the performance obtained by commercial preprocessors capable of restructuring code to exploit the memory hierarchy.